A Mutable Log

ARM Development

This post contains some notes on ARM development resulting from participating in a 3-day training course in Austin, Texas.

ARM Architecture

About ARM

ARM based SoC

Processor terminology – with cache

ARM architecture evolution

Data size and instruction sets

Registers and processor modes

Program status register (PSR)

Program counter (PC)

Data alignment

Endianness

Exception handling

Vector table or jump table

0x1C – FIQ

0x18 – IRQ

0x14 – Reserved

0x10 – Abort

0x0C – Prefetch abort

0x08 – Software interrupt

0x04 – Undefined instruction

0x00 – Reset

ARM instruction set

Example data processing instructions

SUB r0, r1, #5
ADD r2, r3, r3, LSL #2
ANDS r4, r4, #0x20
ADDEQ r5, r5, r6

Example branching instruction

B <label>

Example memory access instructions

LDR r0, [r1]
STRNEB r2, [r3, r4]
STMFD sp!, {r4 - r8, lr}

Thumb instruction set

ARM7TDMI processor core

ARM9TDMI

Other families

Development Tools

RVDS

Compiler optimization options

ATPCS

Libraries and Semihosting

C/C++ Hints and Tips

Inlining of functions

Parameter passing

Loops

Division

Floating point

Variable types

Stack issues

Unaligned accesses

Multifile compilation

Useful references

Application Notes and Articles

Books